CONFERENCE & EXHIBITION

FPGA KONGRESS 2019

May 21 - 23, 2019 | Munich | Germany

FPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers.

The event focusses on user-oriented, practically applicable solutions that developers can quickly integrate into their own everyday work.

Take advantage of the combined knowledge of top-class FPGA experts including TRIAS and our partner Bitvis.


Conference Programme - Extract

  • Day 1:

21.05.2019 at 16:30
Espen Tallaksen, Bitvis (English)
Introduction to FPGA VHDL Verification based on UVVM

Advanced FPGA VHDL Verification based on UVVM

  • Day 2: 

22.05.2019 at 14:15
Hans-Jürgen Schwender, TRIAS (German)
Erstellen eines Simulations Testcases

  • Day 2: 

22.05.2019 at 14:15 Uhr
Espen Tallaksen, Bitvis (English)
Making a structured VHDL testbench – for beginners

  • Day 2: 

22.05.2019 at 16:30 Uhr
Hans-Jürgen Schwender, TRIAS (German)
SystemVerilog – smarte Features für die FPGA (VHDL) Design Verifikation

  • Day 2: 

22.05.2019 at 16:30 Uhr
Espen Tallaksen, Bitvis (English)
Making an advanced testbench using models, scoreboards, verification components, high level transactions and more

  • Day 3: 

23.05.2019 at 09:45 Uhr
Stefan Bauer, Mentor (English)
Functional Safety for FPGAs

TRIAS will also be participating as an exhibitor during the congress days 21st and 22nd May 2019.
We look forward to your visit and interesting discussions.

More Information Registration