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Technical subjects covering FPGA and IC Design


You are surely familiar with the term Lunch & Learn. However, we have decided to turn it around and learn before lunch.

During our HDL "Frühschoppen" we want to stimulate your grey matter and reward you with a nice lunch, during which you can discuss what you have learned even further.

In cooperation with Mentor - A Siemens Business we are continuing our series of events to inform you about technical subjects in 2019.

The topic for the first HDL "Frühschoppen" in 2019 is “Exhaustive automated formal solutions for FPGA verification challenges”.

Wouldn’t it be great if you could begin serious verification before a testbench was available? Even better - what if your verification process gave you exhaustive results? Formal verification delivers on both counts, and today formal apps enable regular engineers to make use of classical formal techniques to explore their design’s behaviour in an intuitive, interactive manner. Applying formal early shortens the overall verification cycle by finding and fixing most bugs during development instead of late in the verification game. Furthermore formal techniques easily find bugs that are often never found in functional simulation.

During this “Frühschoppen” Stefan Bauer, one of Mentor’s verification experts, will introduce formal techniques to verify clock domain crossing issues, and to find bugs due to common RTL coding errors. Furthermore you will learn how to use Mentor’s formal apps within the FPGA vendor tools like Xilinx Vivado or Intel Quartus.

To complete the tutorial for the brain, something for the stomach and general well-being will be served.


5th February 2019


Schlachthofstraße 2

70188 Stuttgart


6th February 2019

"Alter Bahnhof" Oberkassel

Belsenplatz 2

40545 Düsseldorf - Oberkassel


  • 10:30 Registration / Welcome
  • 11:00 Technical Presentation
  • 12:30 Lunch (Networking, Q & A)
  • Open ended / expected end 14:30

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