TRIAS Training Center

Progress through continuing education

  • 14. December 2023

With increasingly complex designs, it is becoming more and more difficult to develop FPGAs efficiently and test them reliably using conventional methods in order to find errors at an early stage of development.

For this reason, it makes sense to use software that reliably supports you at all stages of FPGA Design and FPGA Verification and makes the development process more efficient - while at the same time improving quality!

Continuing education is an important topic for us, this is why we train our customers in innovative design and verification processes as well as in the use of our EDA and ECAD solutions.

Through intensive and competent consulting, tailor-made solutions and further training, we ensure digitalization in product development - for shorter development times, improved quality and increased reliability.

This is how we support you in your digital transformation.

Our workshop offerings  - register now!

Click on the image to learn more about each course:

The course is aimed at FPGA and digital ASIC designers who want to work smarter and more efficiently and develop their products with higher quality. It will be shown how to optimize and accelerate the development and also improve the quality of the design.

The workshop is aimed at FPGA designers and gives an overview of the SystemVerilog language and introduces the new verification methods "Assertion Based Verification", "Constrained-Random-Generation" and "Functions Coverage".

The course is aimed at verification engineers without prior knowledge of UVM who want to start using UVM testbenches.
The objective of the course is to create a complete UVM testbench using the Siemens EDA UVM Framework (UVMF), which is then supplemented in a few places with application-specific code.

This workshop is intended for developers who want to develop high-speed interfaces between semiconductor components and complex high-speed circuits at board level. The training is suitable for developers who not only design schematics, but also layout and systems.

Through the workshop you will get a general introduction to the modern verification method UVVM (Universal VHDL Verification Methodology).After the course, participants will know how to structure an FPGA verification platform, implement their testbenches and write test sequencers,

This workshop is for developers who want to implement high-speed memory interfaces on custom boards. You will learn how to apply signal integrity simulation to optimize high-speed memory interfaces.

The VHDL 2008 workshop provides an overview of the changes and innovations in the language defined in the IEEE 1076-2008 standard. Among other things, the participants will get to know the innovations and improvements of the language for RTL design.

For booking or a quote in advance contact us at +49 (0)2151/95301-0. By clicking on the button you can also contact us by e-mail.