TRIAS Mediathek

Recordings FPGA Verification Day 2023 – Watch now!

  • 11. October 2023

A successful FPGA Verification Day is behind us.

It was a pleasure for us to gather renowned experts from FPGA development and FPGA verification to bring you closer to the possibilities of digitalization in product development.

You could not attend our Online-Event live  or you would to have a look at the presentations again?

All recordings of the FPGA Verification Day are now in our Mediathek.
There you can also find the recordings of the last FPGA Verification Days and our webinar series FPGA Verification Made Modern.

Let's review the fpga verification day 2023:

In his Keynote Dr. Michael Gude has shown the architectural inventions and benefits of GateMate FPGAs. These benefits are protected by 3 patent families, which are already granted in the USA.
Improved LUT-Tree, Routing fabric with advance Switch boxes and IO structure have been shown.

The implementation of a family of FPGAs with only one source wafer is explained.

Debugging is a time-consuming task, in fact most of the time in verification is spent on debugging. This is why it’s important to have a tool that gives you all kinds of support for this task. Questa always had a very good debug environment. Visualizer has been around for a while, as an add-on, but also as the standard UI for the Questa formal apps, like Questa CDC, Questa AutoCheck, Questa Lint etc. Since the 2023.1 release also Questa Prime and Core are shipped with the Visualizer debug environment and licensing has been upgraded to include all necessary features.

Hans-Jürgen Schwender showed the highlights of the new debug capabilities that are available with the Visualizer Debug UI.
Besides showing some of the features in detail he has also presented how the Visualizer UI can be used and what the benefits of using it compared to the Classic debug flow are.

Mitigating disruptive bugs in team projects demands a proactive approach.

In this presentation Faïçal Chtourou showcased Questa tool workflows aligned with Continuous Integration (CI), preventing or eliminating such issues. Participants have learnt how to employ formal and simulation tools synergistically, ensuring robust verification of RTL and testbench changes before team-wide release.

In this presentation Espen Tallaksen has shown the importance of Code coverage, Functional Coverage and Specification Coverage (aka Requirement Coverage) when it comes to ensuring the right quality.
Code coverage is handled by the simulator, and UVVM provides great functionality for Functional Coverage and Specification Coverage.
Specification coverage is getting more and more attention, and is critical for safety (e.g. DO-254) and mission critical (e.g. ESA space) applications. Unfortunately, this is often handled manually, which is really time-consuming and error-prone. UVVM’s Specification coverage allows a very efficient collection of predefined requirements, and it generates the reports you need for both mission-critical and safety projects, and in fact for any project where quality is important.

After his presenation he has shown in his step-by-step demonstrated tutorial, how to make a VHDL testbench using the open source UVVM methodology and library.

He has added UVVM Specification coverage commands to accumulate the Requirement coverage and finally report this in various formats of the Requirements Traceability Matrix (RTM).

Formal verification normally equates to a full Assertion Based Verification (ABV) flow, the adoption of which can be lengthy and costly.

Neil Rattray has demonstrated the aspects of formal which can supplement your existing simulation-based flow.

These are:

o Structural Coverage signoff
Here we are asking the question, how much of the implemented RTL has been checked?

o Functional Coverage signoff
Here we are asking how much of the design functionality has been checked?

o Synthesis and PAR signoff
Here we are asking whether our implemented RTL has been correctly synthesized to our target technology?

Each of these techniques can be adopted with low risk and effort, but will provide greater assurance of the design flows. Join this session to hear how this will help you.

Following FPGA vendor Efinix Inc.'s presentation at FPGA Verification Day 2022, Joachim Müller has given an update which focused on what's next for the high-performance Quantum® fabric in the Titanium FPGA family in particular. Successful strategy includes not only technology selection and development, but also continuous evolution of design software, IP, and applications. The presentation ha provided a day-by-day look at what the architecture can do and how it is supported in hardware and software for various application areas.