Also In the last webinar series FPGA Verification Made Modern, renowned experts in the FPGA field presented their methods and solution approaches for verifying the increasingly complex structures of FPGAs quickly and in high quality.
GET TO KNOW THESE METHODS AND TOOLS TOO!
Click on the image to view the webinar:
Hans Tiggler, Senior Application Engineer at Saros Technology explains how to connect a third-party application to Modelsim and Questa using the Foreign Language Interface.
How can you avoid errors in safety-critical systems that lead to damage or even loss of life? Learn more about safe verification in the context of DO-254 from Rachid Laaris, Product Manager at CADLOG.
Detecting errors early in the development process means improving RTL quality! Faïçal Chtourou, Field Application Engineer at Siemens EDA shows how to use Questa Lint in a continuous integration flow.
Espen Tallaksen, EmLogic gives an introduction to UVVM as the fastest growing FPGA verification method. Learn how you too can improve FPGA quality and development time easily and simply.
How can you ensure that data from one clock domain is correctly transferred to another?
Hans-Jürgen Schwender, Technical Manager at TRIAS mikroelektronik, gives you the answer to this question!