FPGA DESIGN | IC DESIGN

DESIGN CREATION & -REUSE

Design Creation

Whether designing an FPGA or ASIC, the devices have advanced capabilities and complex features that, when put under tight development cycles, burden the design teams to produce efficient and robust chips. Hence, the design teams have placed more demands on HDL processes, automation, and style guidelines for developing quality design results.

Standard languages (such as VHDL, Verilog, SystemVerilog) and IP formats, along with common industry version management systems aid in producing repeatable and dependable design processes, but the tools that utilize these standards need to do much more than edit text files. Mentor Graphics delivers a complete design solution for FPGA and ASIC HDL development beginning with comprehensive design creation addressing new code creation, formal and informal design reuse, and any combination in between. These HDL design capabilities greatly assist engineers, individuals and teams, in creating, analysing, and managing their complex designs, improving their productivity and accelerating design creation.

Design Reuse

Effective design reuse is a critical objective for every electronic design company as 75% of future productivity gains will come through reuse. Executives, managers, and engineers all have a big stake in reuse, but nearly everyone underestimates the challenges associated with it.

Mentor Graphics offers products in the HDL Designer Series family that will, in minutes, automatically comprehend the design hierarchy, highlight syntax errors, point out missing or orphaned blocks and determine the quality of the HDL code.  It will visualize the design to accelerate understanding of the design being reused, and prepare the new design for efficient future reuse, optionally in IP-XACT format.

Product Solutions

HDL DESIGNER

HDL Designer

Source: Mentor hds_datasheet_mgc_7-18
HDL Designer is a powerful HDL-based environment used by individual engineers and engineering teams worldwide to analyse, create and manage complex FPGA and ASIC designs.

HDL Designer is a powerful HDL-based environment which delivers new approaches to design today’s most complex FPGAs and ASICs. HDL Designer is used worldwide by individual engineers and engineering teams to create, analyse and manage the design of these amazing devices.

HDL Designer accelerates the productivity and predictability of the project by automating many flows and tasks. Automated rule checking, register generation and documentation and the powerful text, tabular and graphical creation editors save incredible amounts of engineering time and can minimize manually introduced errors. Tool integration and version management of the entire project help keep the team, tools and design process structured, but is still flexible enough through an API to augment existing design flows. Through this automation and project management, the overall quality of the project and resulting chip is improved and project risk greatly reduced.

By using HDL Designer, savings and cost avoidance can be recognized immediately through this automation and will continue with future projects through better design reuse, consistency of coding and improved documentation. For safety- and mission-critical projects, HDL Designer’s design checking, version management, register generation and documentation support adherence to regulatory compliance mandates such as DO-254, ISO 26262 and others more.

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How is the MAC address generated?

Windows
Start a command shell by typing: cmd in the Windows menu search box and then Enter. A command line window opens. Enter: ipconfig /all. All your system network adapters will be listed. Find an adapter with a network connection and copy the physical address. This consists of 6 x 2-digit hexadecimal numbers separated by hyphens.

Linux/Unix
Open a terminal and enter the following command: ifconfig. Confirm with Enter.
Look for the network eth0, depending on distribution it can also have a different name. The line with ether specifies the MAC ID: Here are 6 x 2-digit hex numbers separated by a colon.

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Visual Elite HDL

Visual Elite is built upon a strong HDL implementation infrastructure while offering the most advanced electronic system-level (ESL) and transaction level modelling (TLM) concepts and mechanisms.

Continuous Design Flow from TLM to RTL

SystemC TLM blocks, VHDL and Verilog Blocks, and even software blocks in embedded systems all need to be managed and integrated into one system that should be verified and taken gradually into implementation.

Visual Elite offers a variety of languages and design entry methods allowing the user to select the best suited approach for their modelling needs. Visual Elite supports both text-based and graphical entry, including block diagrams, state diagrams and connectivity tables. Designers can use VHDL, Verilog, SystemC or any combination of these to design and build products.

Visual Elite allows distributed design teams efficient control and management of the entire design process. Built-in documentation and reuse features, such as text-to-graphics transformation, simplify design management. The design infrastructure for data and project management enables team leaders to enforce a consistent design flow and methodology. The documentation capability enables chip architects and designers to share ideas and design requirements, including hierarchical views within HTML, and links into Microsoft OLE and FrameMaker.

Visual Elite can link with existing mixed-language designs and offer cross language model distribution, including mapping SystemC RTL into HDL. Model generation can be tailored to various SystemC and HDL synthesis tools and allows single source modeling. Visual Elite supports custom modules from tools such as SPW, Matlab, and popular FPGA core libraries.

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