Whether designing an FPGA or ASIC, the devices have advanced capabilities and complex features that, when put under tight development cycles, burden the design teams to produce efficient and robust chips. Hence, the design teams have placed more demands on HDL processes, automation, and style guidelines for developing quality design results.
Standard languages (such as VHDL, Verilog, SystemVerilog) and IP formats, along with common industry version management systems aid in producing repeatable and dependable design processes, but the tools that utilize these standards need to do much more than edit text files. Siemens EDA, formerly Mentor Graphics, delivers a complete design solution for FPGA and ASIC HDL development beginning with comprehensive design creation addressing new code creation, formal and informal design reuse, and any combination in between. These HDL design capabilities greatly assist engineers, individuals and teams, in creating, analysing, and managing their complex designs, improving their productivity and accelerating design creation.
Effective design reuse is a critical objective for every electronic design company as 75% of future productivity gains will come through reuse. Executives, managers, and engineers all have a big stake in reuse, but nearly everyone underestimates the challenges associated with it.
Siemens EDA offers products in the HDL Designer Series family that will, in minutes, automatically comprehend the design hierarchy, highlight syntax errors, point out missing or orphaned blocks and determine the quality of the HDL code. It will visualize the design to accelerate understanding of the design being reused, and prepare the new design for efficient future reuse, optionally in IP-XACT format.