IC DESIGN

PHYSICAL AND CIRCUIT VERIFICATION

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Physical Verification

Calibre® nmDRC and Calibre® nmLVS are the market share leaders in physical verification. Calibre® also leads the market with innovative features such as incremental DRC, which ensures you can complete your design rule checking quickly and efficiently, and equation-based design rules, which let designers define continuous, three-dimensional functions that accurately and precisely reflect the complex physical interactions of today's nanometer designs.

Product Solutions

Calibre® nmLVS

Caliber® nmLVS is the market-leading layout vs. schematic physical verification tool. Thightly linked with Caliber® nmDRC and Caliber® xRC ™, it delivers a production-proven solution for the physical verification and parasitic extraction of nanometer IC designs.

Calibre® nmLVS performs a vital function as a member of a complete IC verification tool suite by providing device and connectivity comparisons between the IC layout and the schematic. Calibre's hierarchical processing engine runs Calibre® nmLVS, supplying data for modifying the IC design to achieve superior functionality and reliability.

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Calibre® nmDRC

Total cycle time is on the rise due to more complex and larger IC designs, higher error counts and more verification iterations. Calibre® nmDRC responds to the need for reduced cycle time with revolutionary new capabilities that differentiate Calibre nmDRC substantially from traditional DRC tools.

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Calibre® Pattern Matching

Calibre® Pattern Matching supplements multi-operational text-based design rule checks with an automated visual geometry capture and compare process. This visual approach is not only powerful in its ability to capture complex pattern relationships simply and quickly, but also easy to incorporate into mixed tool flows—enabling users to easily create new applications solving difficult problems. As part of the Calibre® nmPlatform, Calibre® Pattern Matching is used in conjunction with a wide range of other Calibre® tools to solve complex layout issues with ease across design, manufacturing, and wafer test.

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Calibre® Auto-Waivers

Calibre® Auto-Waivers™ provides automated recognition and removal of waived design rule violations during DRC. Calibre® Auto-Waivers not only eliminates costly time and effort from the verification process, but also ensures accurate processing of all waiver information on every DRC run. Reducing design verification time while simultaneously improving the quality of results can provide the market edge you need to stay ahead of your competition.

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Calibre® Interactive

Calibre® Interactive™ is the invocation GUI for Calibre® DRC™, LVS and xRC™ tools for physical verification and parasitic extraction. It’s easily accessed from the menu bar within popular layout design environments.

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Calibre® RVE

Debugging the error results of physical and circuit verification is costly, both in time and resources. Calibre® RVE provides fast, flexible, easy-to-use graphical debugging capabilities that minimize your turnaround time and get you to “tapeout-clean” on schedule. Better yet, Calibre® RVE easily integrates into all popular layout environments, so no matter which design environment you use, Calibre® RVE provides the debugging technology you need for fast, accurate error resolution.

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Calibre® DESIGNrev

With design size and complexity increasing, traditional layout editors lack the capability to quickly and efficiently visualize, revise and stream-out layout data. Calibre® DESIGNrev™ speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS® files.

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Calibre® RealTime Custom

On-Demand Calibre signoff verification in custom/AMS design

The Calibre® RealTime Custom interface enables on-demand Calibre signoff design rule checking (DRC) for custom and analog /mixed-signal (AMS) design flows, improving both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance.

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Calibre® RealTime Digital

On-Demand Calibre signoff verification in P&R

The Calibre® RealTime Digital interface enables on-demand immediate Calibre signoff design rule checking (DRC) for digital design flows, enabling physical design and verification engineers to shave weeks off their tapeout schedule. Providing significant productivity advantages for “last mile” manual DRC closure, the Calibre® RealTime Digital interface enables digital designers to optimize their manual DRC fixes and focus on meeting their power, performance and area (PPA) goals.

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Calibre® 3DSTACK

Calibre® 3DSTACK extends Calibre® die-level signoff verification to enable complete signoff verification of a wide variety of 2.5D and 3D stacked die assemblies. With Calibre® 3DSTACK, designers can perform signoff DRC and LVS checking of complete multi-die systems at any process node without breaking current tool flows or requiring new data formats, significantly reducing time to tapeout. Because 3DSTACK is enabled using standard Calibre® DRC, Calibre® LVS and Calibre® DESIGNrev license features, no new licenses or tools are required.

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Circuit Verification

Circuit Verification involves several essential steps in the design process that will help identify potential circuit or design errors as well as extract the necessary data for downstream circuit simulation. During this step, layout is analysed and compared vs. the schematic to ensure design integrity. Second, the design is analysed for short-term and long-term electrical failures and, if found, those are presented to the designer for fixing.

And finally, a detailed silicon model is constructed with intentional device, advanced parameters, and parasitic information into a format that consumed by a downstream simulator so that designers can reliably determine if their design is meeting electrical specifications (timing, power, etc.)

Product Solutions

Calibre® xACT

Calibre® xACT™ delivers high performance parasitic extraction for digital, custom, analog and RF designs. With its integrated fast 3D field solver and highly parallel architecture, Calibre xACT provides attofarad accuracy with the performance needed for multi-million instance designs.

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Calibre® xACT 3D

Calibre® xACT 3D features a 3D field solver modelling engine built on advanced software algorithms to accurately calculate parasitic effects at the transistor level. Using Calibre® xACT 3D on a multi-CPU platform makes extraction turnaround time competitive with the rule-based tools, shortening design cycle times.

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Calibre® nmLVS

Caliber® nmLVS is the market-leading layout vs. schematic physical verification tool. Thightly linked with Caliber® nmDRC and Caliber® xRC ™, it delivers a production-proven solution for the physical verification and parasitic extraction of nanometer IC designs.

Calibre® nmLVS performs a vital function as a member of a complete IC verification tool suite by providing device and connectivity comparisons between the IC layout and the schematic. Calibre's hierarchical processing engine runs Calibre® nmLVS, supplying data for modifying the IC design to achieve superior functionality and reliability.

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Calibre® PERC

Calibre® PERCreliability verification solution is designed to address your advanced circuit verification needs for electrostatic discharge (ESD), electrical overstress (EOS), signals crossing multiple power domains, advanced ERC and other reliability concerns.

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Calibre® xRC

Calibre® xRC™ is a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation. Calibre® xRC is able to extract interconnect parasitics hierarchically.

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Calibre® xL

Calibre® xL offers designers full-chip, fast, and accurate extraction of frequency dependent loop inductance and loop resistance and automatically accounts for return path change with frequency.

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