FPGA DESIGN

SIMULATION & VERIFICATION

Product Solutions

ModelSim®

Modelsim® HDL simulator provides FPGA customers with and easy cost-effective ways to speed up FPGA development.

In addition to supporting standard HDLs, ModelSim® increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.

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Source: Mentor - A Siemens Business

ModelSim

The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. You can edit, recompile, and re-simulate without leaving the ModelSim® environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim® simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).

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MODELSIM PE®

  • VHDL, Verilog and SystemVerilog
  • SystemC option available
  • Intelligent, easy-to-use  GUI with Tcl interface
  • Advanced Code Coverage and analysis
  •  Standard support for Xilinx SecureIP

Advanced Code Coverage

ModelSim’s advanced code coverage capabilities and ease of use lower the barriers for leveraging this valuable verification resource.

The ModelSim advanced code coverage capabilities provide valuable metrics for systematic verification. All coverage information is stored in the Unified Coverage DataBase (UCDB), which is used to collect and manage all coverage information in a highly efficient database. Coverage utilities that analyse code coverage data, such as merging and test ranking, are available. Coverage results can be viewed interactively, post-simulation, or after a merge of multiple simulation runs.

The coverage types supported include:

  • Statement Coverage
  • Branch Coverage
  • Condition Coverage
  • Expression Coverage
  • Focused Expression Coverage
  • Enhanced Toggle Coverage
  • Finite State Machine Coverage

Memory window

The memory window allows intuitive and flexible viewing and debugging of design memories.

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How is the MAC address generated?

Windows
Start a command shell by typing: cmd in the Windows menu search box and then Enter. A command line window opens. Enter: ipconfig /all. All your system network adapters will be listed. Find an adapter with a network connection and copy the physical address. This consists of 6 x 2-digit hexadecimal numbers separated by hyphens.

Linux/Unix
Open a terminal and enter the following command: ifconfig. Confirm with Enter.
Look for the network eth0, depending on distribution it can also have a different name. The line with ether specifies the MAC ID: Here are 6 x 2-digit hex numbers separated by a colon.

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MODELSIM DE®

  • VHDL, Verilog, PSL and SystemVerilog 
  • SystemC option available
  • Intelligent, easy-to-use GUI with Tcl interface
  • Advanced Code Coverage and analysis
  • Assertion-Based verification
  • Standard support for Xilinx SecureIP
Assertion Thread Viewer

Source: Mentor ModelSim® DE_datasheet_mgc_07-17
The Assertion Thread Viewer shows a complete assertion evaluation identifying why each thread passes or fails.

Assertion-based Verification with SystemVerilog Assertion and PSL

​Assertion-based verification (ABV) improves design quality through the insertion of white-box monitors that provide a window allowing active monitoring of functional correctness.

Assertion Thread Viewer und Assertion Browser

ModelSim® DE includes an innovative Assertion Thread Viewer, which graphically shows the complete evaluation of an activated assertion. Statistics for each assertion can be examined in the Assertion Browser window.

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Privacy Policy*
I have read the TRIAS mikroelektronik GmbH privacy policy and I agree that my details and data are collected and stored electronically in order to answer my request.

Fields marked with * are mandatory.

How is the MAC address generated?

Windows
Start a command shell by typing: cmd in the Windows menu search box and then Enter. A command line window opens. Enter: ipconfig /all. All your system network adapters will be listed. Find an adapter with a network connection and copy the physical address. This consists of 6 x 2-digit hexadecimal numbers separated by hyphens.

Linux/Unix
Open a terminal and enter the following command: ifconfig. Confirm with Enter.
Look for the network eth0, depending on distribution it can also have a different name. The line with ether specifies the MAC ID: Here are 6 x 2-digit hex numbers separated by a colon.

Privacy Policy*
I have read the TRIAS mikroelektronik GmbH privacy policy and I agree that my details and data are collected and stored electronically in order to answer my request.

Fields marked with * are mandatory.

ModelSim® combined with HDL Designer® provides a complete design environment with advanced project management and visualisation capabilities.

Easy transition from ModelSim® to Questa®

ModelSim® has a common frontend and user interface with Mentor’s flagship simulator Questa®. For example, customers can easily upgrade to Questa® for increased performance and support for advanced verification features.