FPGA VERIFICATIoN DAY 2023
26th of September, 2023 09:00 AM - 05:00 PM CET
NOW ONLINE | NOT ON SITE
We have received increasing feedback from our customers that it is difficult to participate in a one-day live event due to internal company reasons or travel restrictions.
Since we want to give a larger circle the opportunity to participate in the technical presentations of renowned experts in the field of FPGA development and FPGA verification, we have decided to hold the FPGA Verification Day 2023 now as an ONLINE conference.
Take the opportunity to attend technical presentations by renowned experts in the field of FPGA development and FPGA verification.
The event will be opened with a keynote by Dr. Michael Gude from Cologne Chip.
Well-known experts from Siemens EDA, Efinix, Emlogic and of course TRIAS will round off the program.
As every year, our experts will be on hand for a question-and-answer session - take the opportunity to benefit from the concentrated knowledge.
Participation is free of charge again this year.
Start of the conference is 09:00 AM CET.
End of the conference is 05:00 PM CET.
The Online-Conference will be held via Zoom Webinar.
You will receive your registration link on time before the start of the FPGA Verification Day.
You only need to register once the link is valid for all sessions.
Register now to benefit from the concentrated knowledge in your practice!
People who have already registered to the LIVE-event in Cologne doesn't have to register again. They will get automatically an email with registration link.
Ask the Experts
Get to know our experts:
Dr. Michael Gude
Cologne Chip GmbH
Keynote - GateMate FPGAs Architecture, Features and Applications
The Keynote will show the architectural inventions and benefits of GateMate FPGAs. These benefits are protected by 3 patent families, which are already granted in the USA.
Improved LUT-Tree, Routing fabric with advance Switch boxes and IO structure are shown.
The implementation of a family of FPGAs with only one source wafer is explained.
GateMate uses Yosys as open source HDL synthesis software.
TRIAS mikroelektronik GmbH
Visualizer - Debugging without sacrificing Simulation Performance
Field Application Engineer
Streamlining Verification with Questa Static Tools in CI Flows
Mitigating disruptive bugs in team projects demands a proactive approach. This webinar showcases Questa tool workflows aligned with Continuous Integration (CI), preventing or eliminating such issues. Participants will learn to employ formal and simulation tools synergistically, ensuring robust verification of RTL and testbench changes before team-wide release
Get the right FPGA quality through efficient Specification Coverage
(aka Requirement Coverage)
Code coverage, Functional Coverage and Specification Coverage (aka Requirement Coverage) are all important aspects of verification when it comes to ensuring the right quality. Code coverage is handled by the simulator, and UVVM provides great functionality for Functional Coverage and Specification Coverage.
Specification coverage is getting more and more attention, and is critical for safety (e.g. DO-254) and mission critical (e.g. ESA space) applications. Unfortunately, this is often handled manually, which is really time-consuming and error-prone. UVVM’s Specification coverage allows a very efficient collection of predefined requirements, and it generates the reports you need for both mission-critical and safety projects, and in fact for any project where quality is important.
This presentation briefly explains Functional coverage (and randomisation) before it goes into depth on Specification Coverage. It also shows what is provided with UVVM and how this could be applied. UVVM is free and Open Source, and so are all the interface models, randomisation, functional coverage and specification coverage.
Demonstrated step-by-step tutorial on making a testbench for proper Specification Coverage (aka Requirement Coverage)
This demonstrated tutorial is intended for designers and verification engineers who want to learn how to apply Specification coverage to ensure that all Requirements have been verified. In this step-by-step demonstrated tutorial, we will make a VHDL testbench using the open source UVVM methodology and library.
We will add UVVM Specification coverage commands to accumulate the Requirement coverage and finally report this in various formats of the Requirements Traceability Matrix (RTM).
Please note that material from the previous presentation will not be repeated in this demonstrated tutorial.
Formal for all:
A practical guide to deploying Formal Verification in your Design Environment
Formal verification normally equates to a full Assertion Based Verification (ABV) flow, the adoption of which can be lengthy and costly. There are aspects of formal which can supplement your existing simulation-based flow. These are:
o Structural Coverage signoff
Here we are asking the question, how much of the implemented RTL has been checked?
o Functional Coverage signoff
Here we are asking how much of the design functionality has been checked?
o Synthesis and PAR signoff
Here we are asking whether our implemented RTL has been correctly synthesized to our target technology?
Each of these techniques can be adopted with low risk and effort, but will provide greater assurance of the design flows. Join this session to hear how this will help you.
Expansion of the FPGA family: Growing demands on the ECO system
Following FPGA vendor Efinix Inc.'s presentation at FPGA Verification Day 2022, this update focuses on what's next for the high-performance Quantum® fabric in the Titanium FPGA family in particular. Successful strategy includes not only technology selection and development, but also continuous evolution of design software, IP, and applications. The presentation will provide a day-by-day look at what the architecture can do and how it is supported in hardware and software for various application areas.