26th of September, 2023  09:00 AM - 05:00 PM CET 

A successful event is behind us.

It was a pleasure for us to gather renowned experts from FPGA development and FPGA verification to bring you closer to the possibilities of digitalization in product development.

Did you miss one or the other presentation or would you like to have a look at the presentations again?

All recordings of the FPGA Verification Day are now in our Mediathek.
There you can also find the recordings of the last FPGA Verification Days and our webinar series FPGA Verification Made Modern.

Let's review the FPGA Verification Day 2023

Dr. Michael Gude
Cologne Chip GmbH

Keynote - GateMate FPGAs Architecture, Features and Applications

The Keynote will show the architectural inventions and benefits of GateMate FPGAs. These benefits are protected by 3 patent families, which are already granted in the USA.
Improved LUT-Tree, Routing fabric with advance Switch boxes and IO structure are shown.
The implementation of a family of FPGAs with only one source wafer is explained.
GateMate uses Yosys as open source HDL synthesis software.


Michael Gude achieved a Diploma and Dr. degree from the University of Aachen (RWTH) in electrical engineering. He was involved in research and development from the early days of microprocessors. Michael is founder and CEO of several technology oriented companies; one of them Cologne Chip AG, which was started in 1995.
Already in 1989 Michael used the first FPGAs from Actel.
Cologne Chip is well known for telecommunication chips since more than 20 years.
Now offering their latest developments, the GateMate FPGA family.

Michael holds a bunch of patents all over the world.

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Hans-Jürgen Schwender
Technical Manager
TRIAS mikroelektronik GmbH

Visualizer - Debugging without sacrificing Simulation Performance

Debugging is a time-consuming task, in fact most of the time in verification is spent on debugging. This is why it’s important to have a tool that gives you all kinds of support for this task. Questa always had a very good debug environment.Visualizer has been around for a while, as an add-on, but also as the standard UI for the Questa formal apps, like Questa CDC, Questa AutoCheck, Questa Lint etc. Since the 2023.1 release also Questa Prime and Core are shipped with the Visualizer debug environment and licensing has been upgraded to include all necessary features.
This presentation is a highlight of new debug capabilities that are available with the Visualizer Debug UI.
Besides showing some of the features in detail it will also be presented how the Visualizer UI can be used and what the benefits of using it compared to the Classic debug flow are.


Hans-Jürgen Schwender has a masters degree in electrical engineering. From 1991 until the end of 2001, he worked as an ASIC design engineer at Philips Kommunikationsindustrie and Lucent Technologies in Nuremberg and at Infineon Technologies in San Jose, CA, USA. He worked on the creation of specifications, the implementation in VHDL, verification on module and chip level as well as programming of ASIC Driver Software in C.

 Mr. Schwender has been working at TRIAS mikroelektronik GmbH since 2002 and, as the technical manager covers a large part of Siemens EDA's products - with a focus on HDL design, verification and cable harness design products.

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Faïçal Chtourou

Faïçal Chtourou
Field Application Engineer
Siemens EDA

Siemens Logo

Streamlining Verification with Questa Static Tools in CI Flows

Mitigating disruptive bugs in team projects demands a proactive approach. This webinar showcases Questa tool workflows aligned with Continuous Integration (CI), preventing or eliminating such issues. Participants will learn to employ formal and simulation tools synergistically, ensuring robust verification of RTL and testbench changes before team-wide release


Faïçal Chtourou is an European application engineer at Siemens EDA, specialized in Digital functional verification tools and methodology.

His background includes 10+ years of experience verifying complex SOC in various markets (HPC, Automotive, Flash memory); he has a strong interest in flow automation and RTL quality improvement. Faïçal holds an MS degree in Microelectronics and Telecommunication from Polytech Marseille, France.

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Espen Tallaksen
CEO and founder

Get the right FPGA quality through efficient Specification Coverage
(aka Requirement Coverage)

Code coverage, Functional Coverage and Specification Coverage (aka Requirement Coverage) are all important aspects of verification when it comes to ensuring the right quality. Code coverage is handled by the simulator, and UVVM provides great functionality for Functional Coverage and Specification Coverage.
Specification coverage is getting more and more attention, and is critical for safety (e.g. DO-254) and mission critical (e.g. ESA space) applications. Unfortunately, this is often handled manually, which is really time-consuming and error-prone. UVVM’s Specification coverage allows a very efficient collection of predefined requirements, and it generates the reports you need for both mission-critical and safety projects, and in fact for any project where quality is important.

This presentation briefly explains Functional coverage (and randomisation) before it goes into depth on Specification Coverage. It also shows what is provided with UVVM and how this could be applied. UVVM is free and Open Source, and so are all the interface models, randomisation, functional coverage and specification coverage.

Demonstrated step-by-step tutorial on making a testbench for proper Specification Coverage (aka Requirement Coverage)

This demonstrated tutorial is intended for designers and verification engineers who want to learn how to apply Specification coverage to ensure that all Requirements have been verified. In this step-by-step demonstrated tutorial, we will make a VHDL testbench using the open source UVVM methodology and library.

We will add UVVM Specification coverage commands to accumulate the Requirement coverage and finally report this in various formats of the Requirements Traceability Matrix (RTM).

Please note that material from the previous presentation will not be repeated in this demonstrated tutorial.


Espen Tallaksen is the author and architect of the Universal VHDL Verification Methodology (UVVM), founder of previous Bitvis, and now CEO of EmLogic, the leading FPGA design centre in Scandinavia.
Espen graduated from the University of Glasgow (Scotland) in 1987 and has 30 years’ experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway. During twenty years Espen has had a special interest in methodology cultivation for pragmatic efficiency and quality improvement. UVVM is a result of this.

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Neil Rattray
FAE Manager
Siemens EDA

Formal for all:
A practical guide to deploying Formal Verification in your Design Environment

Formal verification normally equates to a full Assertion Based Verification (ABV) flow, the adoption of which can be lengthy and costly. There are aspects of formal which can supplement your existing simulation-based flow. These are:

o             Structural Coverage signoff
               Here we are asking the question, how much of the implemented RTL has been checked?

o            Functional Coverage signoff
               Here we are asking how much of the design functionality has been checked?

o             Synthesis and PAR signoff
                Here we are asking whether our implemented RTL has been correctly synthesized to our target technology?

Each of these techniques can be adopted with low risk and effort, but will provide greater assurance of the design flows. Join this session to hear how this will help you.


Neil Rattray is a Field Application Engineering Manager for Formal Verification products at Siemens EDA and has over 20 years of experience in EDA, supporting both design and verification flows. Neil runs a team of Formal Verification experts across Europe and leads by example so still remains highly technical, working closely with key customers.

Neil’s deep technical knowledge came from working as both a designer and field application engineer. He started his career as a hardware design engineer but later moved to application engineering, supporting FPGA products, before ultimately making the leap to EDA. Neil cultivates strong relationships with Formal users and has a passion for driving their success with the superior level of support he provides. 

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Joachim Müller
FAE Manager

Expansion of the FPGA family: Growing demands on the ECO system

Following FPGA vendor Efinix Inc.'s presentation at FPGA Verification Day 2022, this update focuses on what's next for the high-performance Quantum® fabric in the Titanium FPGA family in particular. Successful strategy includes not only technology selection and development, but also continuous evolution of design software, IP, and applications. The presentation will provide a day-by-day look at what the architecture can do and how it is supported in hardware and software for various application areas.


Upon graduating at TU Braunschweig in 1989, Joachim Müller held positions in ASIC development, sales and marketing, before joining Lattice Semiconductor in October 2000 as Senior FAE.

Since October 2021 he is in charge of Field Application, Europe, for Efinix Inc.

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