Efficiency and quality is all a question of overview, readability, extensibility, maintainability and reuse, - and a good architecture is the answer. This applies for both Design and Verification.
This course contains a general introduction to modern verification methodology and to UVVM (Universal VHDL Verification Methodology) – the world-wide #1 VHDL-FPGA verification methodology, and also the fastest growing verification methodology independent of HDL.
On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with minor adjustments. In this course you will learn how to reduce development time and at the same time improve the quality.
After the course, participants will know how to structure an FPGA verification platform, how to implement their testbenches, and how to write test sequencers, which can be understood by software and hardware developers. Participants will also learn how to use the complete VHDL-based UVVM verification platform within their own organization
is the CEO and founder of the newly established EmLogic and previously also Bitvis, both independent design centres for embedded software and FPGA, - with Bitvis as a leading Nordic company within its field and EmLogic soon to be. He graduated from the University of Glasgow (Scotland) in 1987 and has 30 years’ experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway. During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement.
One result of this interest is the UVVM verification platform that is the #1 VHDL verification methodology and library world-wide, and in fact the fastest growing FPGA verification methodology independent of HDL.
He has given many presentations and keynotes internationally on various technical aspects of FPGA development, including lots of hands-on tutorials and presentations at FPGA-Kongress every year since 2016; - all with a crowded audience and great feedback. He is also giving courses world-wide on how to design and verify FPGAs more efficiently and with a better quality.
Requirements: Knowledge of the language VHDL I Duration: 5 days - 9 AM - 13:30 PM I Language: English I Price: 2.100,00 EUR net