Training

Accelerating FPGA VHDL Verification

Description

A significant part of the time for any FPGA project is taken up by verification. Reducing this time will accelerate the entire project development. The key to this is a well-structured testbench. This course focuses on FPGA verification and teaches how to build a testbench in a structured way. Theory alternates with practical examples and hands-on tutorials. It also covers important topics such as coverage, BFMs, debugging and randomization. This is also a great opportunity to get acquainted with the "Universal VHDL Verification Methodology" (UVVM), which is freely accessible as open source, allowing a well structured testbench to be easily and quickly created.

Course objectives

After the course participants will know how to structure an FPGA verification platform, implement testbenches, and write test sequencers so software and hardware developers can understand them. They will also learn to apply the complete VHDL-based UVVM verification platform in their organization.

Requirements: Knowledge of the language VHDL I Duration: 3 days I Language: English I Price: 1.850,00 EUR net

Dates

  • 11. - 13.06.2019 | 9am – 5pm | Düsseldorf, Germany

We are happy to offer further options such as live online sessions and on-site training upon request.

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