ModelSim /Questa Core: HDL Simulation teaches users new to using ModelSim or Questa SIM for HDL simulation how to effectively use ModelSim/Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs.
CONTENT I GOALS
- Support of HDL behavioral simulations
- Basic concepts in the digital design flow
- Introduction on how to invoke the Visualizer debug environment
- Hands-on lab exercises
has a masters degree in electrical engineering. From 1991 until the end of 2001, he worked as an ASIC design engineer at Philips Kommunikationsindustrie and Lucent Technologies in Nuremberg and at Infineon Technologies in San Jose, CA, USA. He worked on the creation of specifications, the implementation in VHDL, verification on module and chip level as well as programming of ASIC Driver Software in C.
Mr. Schwender has been working at TRIAS mikroelektronik GmbH since 2002 and, as the technical manager covers a large part of Siemens EDA's products - with a focus on HDL design, verification and cable harness design products.
Requirements: Some VHDL or Verilog knowledgeI Some familiarity with digital design concept I Duration: 1 Day I Language: English / optional German I Price: Upon request