TRAINING

Signal integrity for Hardware Designer

​DESCRIPTION

​This workshop is aimed at developers who want to develop high-speed interfaces between semiconductor components and complex board-level high-speed circuits. The training is suitable for developers who not only design schematics, but also systems and layout. They will learn to judge when signal integrity becomes important and relevant, e.g. to select the appropriate termination procedure. Signal reflection and crosstalk effects are described and demonstrated by simulation. Simulation examples are also demonstrated for common memory interfaces. You will learn how to implement high-speed bus systems, including clock design, load and signal termination. In addition, the power distribution and short circuits in the design are important issues.

Agenda 2​-day Training

  • ​Introduction to Signal Integrity (SI)
  • ​IC to IC timings
  • ​IBIS models for SI simulation
  • ​Transmission lines
  • ​Reflections
  • ​Crosstalk
  • ​SI analysis at the system level
  • Power ​Integrity (PI)
  • Board ​layout guidelines
  • SI ​measuring method


Optional day I 3-day training

​As an optional training module the topics signal integrity issues and solutions for high-speed memory interfaces and serial transceiver links can be offered.

THE TRAINER

Dr.-Ing. Jürgen Wolde

studied theoretical electrical engineering graduated with a degree in engineering. He then completed his doctorate in the field of electromagnetic compatibility to become a Doctor of Engineering. This followed the transition into the industry, where he worked until 2005 in communications engineering at Alcatel. The scope ranged from ASIC design for products, to assembly designs and complex research designs using FPGAbased boards. Collaboration on a variety of studies and research projects and management activities rounded off the range of applications.

He has been self-employed since 2006 and has become a long-time partner of the PLC2, TRIAS and other companies, where he works as a technical trainer worldwide.

Jürgen Wolde is also the co-author of numerous presentations and scientific publications as well as co-owner of several patents.

Requirements: Basic knowledge of hardware design I Duration: 2 or 3 days I Language: English / optional German I Price: 1.250,00 EUR net @ 2 days training I 1.850,00 EUR net @ 3 days training

Dates

  • 10 - 12.03.2020 | 9am – 5pm | Berlin, Germany

We are happy to offer further options such as live online sessions and on-site training upon request.

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