This workshop is for developers who want to implement high-speed memory interfaces on custom boards. Memory interfaces are very often used, they are faster and faster - and design problems are becoming more and more challenging. The training is suitable for developers who design not only schematics, but also systems and layout. You will become familiar with the peculiarities of memory modules for logical and physical designs. Time and voltage tolerances are discussed. You will learn how to use signal integrity simulation to optimize the high-speed memory interfaces. IBIS models and simulation will reveal the effects and possible problem areas. You will learn how to implement high-speed memory slots, including on-board topics. In addition, the power supply problems are discussed. Finally, you will get to know board-level verification options.
- Overview of the types of memory ICs
- Details of DDRx memory devices
- Memory Controller
- Memory interface design
- Brief introduction to signal integrity
- Fundamentals of SI simulation of memory interfaces
- SI simulation options for storage interfaces
- Improved design tolerances through simulation
- Verification of storage interfaces
- Design guidelines for the storage interface
Dr.-Ing. Jürgen Wolde
studied theoretical electrical engineering graduated with a degree in engineering. He then completed his doctorate in the field of electromagnetic compatibility to become a Doctor of Engineering. This followed the transition into the industry, where he worked until 2005 in communications engineering at Alcatel. The scope ranged from ASIC design for products, to assembly designs and complex research designs using FPGAbased boards. Collaboration on a variety of studies and research projects and management activities rounded off the range of applications.
He has been self-employed since 2006 and has become a long-time partner of the PLC2, TRIAS and other companies, where he works as a technical trainer worldwide.
Jürgen Wolde is also the co-author of numerous presentations and scientific publications as well as co-owner of several patents.
Requirements: Hardware design basic knowledge I Duration: 2 days I Language: English I optional German I Price: 1.400,00 EUR net