TRAINING

SystemVerilog – Advanced Verification for FPGA Design

​DESCRIPTION

​This workshop provides an overview about the language SystemVerilog and provides an introduction into the new verification methodologies „Assertion Based Verification“, „Constrained Random Generation“ and „Functional Coverage“.  Participant will learn how to use these powerful verification tools to speed up verification as well as to measure the verification progress and how these methodologies can be naturally applied to the verification of VHDL designs.

​Content I ​Goals

  • ​Basic knowledge of the language SystemVerilog
  • ​Basics in the OOP concept (Object Oriented Programming) in SystemVerilog
  • ​Use of OOP for faster and more efficient, reusable testbench designs
  • ​Knowledge of the concept of an automated testbench
  • ​Introduction to SystemVerilog assertions, constrained randomization, and functional coverage and how they can be integrated into testbenches within a VHDL design context
  • ​Understanding how these concepts help to improve design quality and make verification more efficient


Requirements: HDL experience in verification und design I Duration: 3 days I Language: English / optional German I Price: 1.850,00 EUR net

Dates

  • 12. – 15.03.2019 | 9am – 5pm | Düsseldorf, Germany

We are happy to offer further options such as live online sessions and on-site training upon request.

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