This workshop provides an overview about the language SystemVerilog and provides an introduction into the new verification methodologies „Assertion Based Verification“, „Constrained Random Generation“ and „Functional Coverage“. Participant will learn how to use these powerful verification tools to speed up verification as well as to measure the verification progress and how these methodologies can be naturally applied to the verification of VHDL designs.
Content I Goals
- Basic knowledge of the language SystemVerilog
- Basics in the OOP concept (Object Oriented Programming) in SystemVerilog
- Use of OOP for faster and more efficient, reusable testbench designs
- Knowledge of the concept of an automated testbench
- Introduction to SystemVerilog assertions, constrained randomization, and functional coverage and how they can be integrated into testbenches within a VHDL design context
- Understanding how these concepts help to improve design quality and make verification more efficient
has a masters degree in electrical engineering. From 1991 until the end of 2001, he worked as an ASIC design engineer at Philips Kommunikationsindustrie and Lucent Technologies in Nuremberg and at Infineon Technologies in San Jose, CA, USA. He worked on the creation of specifications, the implementation in VHDL, verification on module and chip level as well as programming of ASIC Driver Software in C.
Mr. Schwender has been working at TRIAS mikroelektronik GmbH since 2002 and, as the technical manager covers a large part of Siemens EDA's products - with a focus on HDL design, verification and cable harness design products.
Requirements: HDL experience in verification und design I Duration: 3 days I Language: English / optional German I Price: 1.995,00 EUR net