TRAINING

SystemVerilog – Advanced Verification for FPGA Design

DESCRIPTION

This workshop provides an overview about the language SystemVerilog and provides an introduction into the new verification methodologies „Assertion Based Verification“, „Constrained Random Generation“ and „Functional Coverage“.  Participant will learn how to use these powerful verification tools to speed up verification as well as to measure the verification progress and how these methodologies can be naturally applied to the verification of VHDL designs.

Content I Goals

  • Basic knowledge of the language SystemVerilog
  • Basics in the OOP concept (Object Oriented Programming) in SystemVerilog
  • Use of OOP for faster and more efficient, reusable testbench designs
  • Knowledge of the concept of an automated testbench
  • Introduction to SystemVerilog assertions, constrained randomization, and functional coverage and how they can be integrated into testbenches within a VHDL design context
  • Understanding how these concepts help to improve design quality and make verification more efficient


The trainer


Alexandru Vlad Velea
has an Electronics, Telecommunications and Information Technology University degree followed by MBA postgraduate degree.

From 2005 on he has been covering mostly the following Siemens products:
• HDL design, simulation and synthesis
• Wiring and harness design

He has a bright knowledge as consultant/ advisor/ technical support/ tools trainer. He is Wiring Harness consultant/ advisor for the Mentor Graphics / Siemens tools since 2011 and Digital IC flow (design/ simulation/ synthesis) consultant/ advisor for the Mentor Graphics/ Siemens tools starting 2005.

TRIAS is an Expert Partner of Siemens Digital Industries Software. Siemens Digital Industries Software awards the status "Expert" to sales partners who have in-depth expert knowledge in a product area or industry and have proven this repeatedly in reference projects.

Alexandru Vlad Velea is certified by Siemens for the products Capital | Capital Essentials (formerly VeSys®) for the automotive and aerospace (Aero) markets and continuously undergoes a mandatory certification program to verify and expand his competencies.


Requirements: HDL experience in verification und design I Duration: 3 days I Language: English / optional German I Price: 1.995,00 EUR net

Dates

  • 15.07. - 17.07.2024 | 9 am – 5 pm | LIVE Online (instructor-led)

We are happy to offer further options such as live online sessions and on-site training upon request.

Course request Request a quote

    Privacy Policy*
    I have read the TRIAS mikroelektronik GmbH privacy policy and I agree that my details and data are collected and stored electronically in order to answer my request.

    Loading...

    Fields marked with * are mandatory.

      Privacy Policy*
      I have read the TRIAS mikroelektronik GmbH privacy policy and I agree that my details and data are collected and stored electronically in order to answer my request.

      Loading...

      Fields marked with * are mandatory.