Training

Verilog for VHDL User

Description

As designs become more complex and development times shrink, development teams increasingly need to leverage IP cores. This means that engineers must become "language-neutral" when dealing with HDL languages.  They need a solid knowledge of VHDL and Verilog and the related design techniques. Our workshop, with its fast and effective method, is suitable for experienced VHDL users to understand the differences, but also the similarities between VHDL and Verilog, and to master the Verilog-specific issues that otherwise could lead to difficult-to-identify problems.

Course objectives

  • Knowledge of Verilog concepts and differences to VHDL
  • Use of Verilog-specific techniques for RTL design
  • Avoiding Verilog pitfalls

Requirements: Digital hardware design basic knowledge   and good knowledge of VHDL I No basic Verilog knowledge required I Duration: 2 days I Language: English / optional German I Price: 1.250,00 EUR net

Dates

  • Dates on request

We are happy to offer further options such as live online sessions and on-site training upon request.

more Information

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