The beginning of a new year is always an occasion to remember nice events of the last year. One highlight at TRIAS was the FPGA Verification Day at the end of September.
LET'S REVIEW FPGA VERIFICATION DAY 2022!
Klicken Sie auf das Bild, um sich die jeweilige Aufzeichnung anzuschauen:
Joachim Müller from Efinix introduces EFINIX® TITANIUM as the latest FPGA family and covers the hardware architecture and how Soft- and Hard-IP can be combined to address a wide range of applications.
Faïçal Chtourou from Siemens EDA explains how the simple Python language can be used as a reusable verification method.
Hans-Jürgen Schwender, Technical Director of TRIAS, presents formal verification and the advantages of this method compared to classical verification.
Neil Rattray from OneSpin: A Siemens Business shows how to avoid systematic design errors from RTL code to the final netlist through formal equivalence checking.
Espen Tallaksen, EmLogic - the father of the VHDL-based verification method UVVM - talks about how randomization can be very useful for modern VHDL testbenches.
In the Q & A session that followed, the panel of experts answered questions that arose.