ModelSim/Questa Core: Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim/Questa Core to effectively and efficiently analyze and debug digital HDL designs.
CONTENT I GOALS
- Using various ModelSim/Questa Core features and techniques
- Produce higher performance test benches
- Produce more reliable device-under-test models
- Develop a greater confidence in simulation thoroughness and completeness
has a masters degree in electrical engineering. From 1991 until the end of 2001, he worked as an ASIC design engineer at Philips Kommunikationsindustrie and Lucent Technologies in Nuremberg and at Infineon Technologies in San Jose, CA, USA. He worked on the creation of specifications, the implementation in VHDL, verification on module and chip level as well as programming of ASIC Driver Software in C.
Mr. Schwender has been working at TRIAS mikroelektronik GmbH since 2002 and, as the technical manager covers a large part of Siemens EDA's products - with a focus on HDL design, verification and cable harness design products.
Requirements: VHDL or Verilog knowledge I Beginner skills in ModelSim/Questa Core or take the ModelSim/ Questa Core: HDL Simulation training class in advance I Duration: 2 Days I Language: English / optional German I Price: Upon request