FPGA VERIFICATION DAY 2021 - 23rd SEPTEMBER 2021
Even though we had hoped to meet you again in Berlin in person, we had to decide against it with a heavy heart. Your and our safety are simply more important.
Therefore FPGA Verification Day 2021 will be an online event again this year. Participation remains of course free of charge.
This year we have again tried our best to put together an interesting and attractive program for you.
Eugen Krassin, who has surely been known to many of you for a long time, will make the start. In his keynote he will report what the future of the Lattice-Nexus platform looks like.
Hans-Jürgen Schwender will go into detail on the subject of clock domain crossing and why it is an important topic in FPGA verification.
The cloud has become an indispensable part of life, and FPGA verification is no exception. David Lidrbauch will address the matter of cloud costs and productivity.
A special highlight is sure to be the presentation by Markus Jäger. As an FPGA developer, he reports on his experience of functional verification with ModelSim.
Of course EspenTallaksen will be with us again, and with it the topic of UVVM and the advantages of this methodology for FPGA verification.
And as every year, at the end of the day, the experts are available for a question and answer session – a great opportunity not to be missed.
Hopefully we will be able to meet in Berlin again next year…..
All presentations in English
Virtual Meeting Room opens
- 08:40 - 09:30
What’s next for the Lattice Nexus platform
Speaker: Eugen Krassin, LEC2
- 10:15- 10:30
- 12:00 - 12:45
UVVM – Brand new features from the world's #1 VHDL Verification Methodology
Speaker: Espen Tallaksen– EmLogic
Ask the Experts - Q & A Session
FPGA Verification Day 2020
The new corona virus has been occupying the world for months now. We have also carefully observed the development of the COVID 19 situation and how it could affect our event.
For everybody’s safety, the FPGA Verification Day 2020 will therefore take place virtually online this year. This is quite exciting. Participation is of course again free of charge.
We would have preferred to welcome you personally in Berlin. Nothing has changed in our efforts to put together a particularly attractive programme for you however.
You can look forward to the latest findings from the Wilson Reseach Group on FPGA Verification Trends, Challenges and Solutions. Harry Foster has evaluated the latest results, and he will present them together with Stefan Bauer.
We can already describe Espen Tallaksen as a regular guest. Of course, he will not be missing this year, he will speak about the topic of UVVM and the reduction of the verification time.
The IEC 62304 standard is a major subject in medical technology, and Tobias Baumann addresses the approval of an FPGA-based medical device. Certainly a topic, which can also be applied to other safety-critical designs.
Hans-Jürgen Schwender explains the integration of a flow requirements management segment and how tracking is achieved, from verification results to coverage metrics reports of the.
Don't miss a single presentation because quiz questions will be asked during the day. The quiz winner has the chance to win a great prize at the end of the day (and no, unfortunately it is not a free Questa license :)).
We hope to meet again in Berlin next year - for our personal networking.
Virtual Meeting Room opens
- 10:30 - 10:45
Coffee Break and first Quiz Questions
Ask the Experts and second Quiz Questions
Quiz Solutions and announcement of the winner
FPGA Verification Day 2019
Everybody is talking about it and many companies are jumping on the functional safety train. The latest industry study from the Wilson Research Group shows, that almost 2/3 of today’s European FPGA design projects are used within a safety application, for example autonomous driving or airplanes.
Such safety applications require a high quality and a high reliability of the FPGAs.
But what is Functional Safety? Functional Safety is driving down the risk of Electrical and Electronics malfunctioning due to failures during operation. Standards like the ISO 26262 or the IEC 61508 focus on two areas of faults: Systematic Faults (try to make sure that your design or a part of your design or the functionality of your design does work correctly according to the specification) and Random HW Faults (EMI or Electro-migration can change the HW behavior). Functional fault testing discovers whether the actual operating behavior of the design under fault conditions is acceptable.
In this one day event, FPGA experts will talk about the functional safety development process with focus on Systematic Faults. Our experts will also be available for your individual questions during an open Q & A Session – and the day ends with a lucky draw and the chance get your hand on an exciting prize (no it’s not a free Questa license :)).
As some of the experts are not familiar with the German language (especially our Bavarian friend Stefan), presentations will be held in English.
Participation is of course free of charge.
26 September 2019 | Berlin | Germany
Select Hotel Berlin Spiegelturm
Ask the Experts followed by Prize Draw