Implementing an FPGA or ASIC design does not just depend on knowing an HDL language. In addition to the knowledge of all language constructs, it is also important to structure the implementation in a suitable manner and to know advantages and disadvantages of different descriptions of the same behavior. If such approaches are consistently used, it will avoid many problems, which take a lot of time for causes to be found and solved, and thus reach their destination faster. The course will show how the development can be optimized and accelerated and also the quality of the design be improved.
- Design architecture and structure
- Clock Domain Crossing (CDC)
- Coding and general digital design
- Design for Reuse
- Reaching the timing requirements
is the CEO and founder of the newly established EmLogic and previously also Bitvis, both independent design centres for embedded software and FPGA, - with Bitvis as a leading Nordic company within its field and EmLogic soon to be. He graduated from the University of Glasgow (Scotland) in 1987 and has 30 years’ experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway. During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement.
One result of this interest is the UVVM verification platform that is the #1 VHDL verification methodology and library world-wide, and in fact the fastest growing FPGA verification methodology independent of HDL.
He has given many presentations and keynotes internationally on various technical aspects of FPGA development, including lots of hands-on tutorials and presentations at FPGA-Kongress every year since 2016; - all with a crowded audience and great feedback. He is also giving courses world-wide on how to design and verify FPGAs more efficiently and with a better quality.
Requirements: Knowledge of FPGA design or digital ASIC design I Duration: 2 days - 9:00 am - 5:00 pm Language: English I Price: 1.350,00 EUR net