Training

Accelerating FPGA and digital ASIC Design

Description

Implementing an FPGA or ASIC design does not just depend on knowing an HDL language. In addition to the knowledge of all language constructs, it is also important to structure the implementation in a suitable manner and to know advantages and disadvantages of different descriptions of the same behavior. If such approaches are consistently used, it will avoid many problems, which take a lot of time for causes to be found and solved, and thus reach their destination faster. The course will show how the development can be optimized and accelerated and also the quality of the design be improved.

Course subjects

  • Design architecture and structure
  • Clock Domain Crossing (CDC)
  • Coding and general digital design
  • Design for Reuse
  • Reaching the timing requirements
  • Quality assurance

Requirements: Knowledge of FPGA design or digital ASIC design I Duration: 2 days I Language: English I Price: 1.250,00 EUR net

Dates

  • 20. - 21.11.2019 | 9am – 5pm | Stuttgart, Germany

We are happy to offer further options such as live online sessions and on-site training upon request.

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