Since the UVM library is very complex, building a testbench from scratch is a time-consuming task and requires a good knowledge of the tools the library provides. In order to help verification engineers to very quickly build a testbench the UVM Framework infrastructure has been developed. With UVM Framework it is possible to very rapidly create a UVM testbench and with a few changes the testbench is ready for simulation within a few hours.
The participants will create a UVM testbench in multiple steps using the UVM Framework After the Workshop participants are able to use the UVM Framework API to create a testbench infrastructure for their own FPGA design.
- Verification - approaches and methodologies
- UVM - fundamentals and principles
- UVM Framework - library components, structure and API
has a masters degree in electrical engineering. From 1991 until the end of 2001, he worked as an ASIC design engineer at Philips Kommunikationsindustrie and Lucent Technologies in Nuremberg and at Infineon Technologies in San Jose, CA, USA. He worked on the creation of specifications, the implementation in VHDL, verification on module and chip level as well as programming of ASIC Driver Software in C.
Mr. Schwender has been working at TRIAS mikroelektronik GmbH since 2002 and, as the technical manager covers a large part of Siemens EDA's products - with a focus on HDL design, verification and cable harness design products.
Requirements: Knowledge in SystemVerilog I Duration: 2 days I Language: English / optional German I Price: 1.250,00 EUR net