Training

UVM Made Easy for FPGA Designer

Description

Since the UVM library is very complex, building a testbench from scratch is a time-consuming task and requires a good knowledge of the tools the library provides. In order to help verification engineers to very quickly build a testbench the UVM Framework infrastructure has been developed. With UVM Framework it is possible to very rapidly create a UVM testbench and with a few changes the testbench is ready for simulation within a few hours.

Course objectives

The participants will create a UVM testbench in multiple steps using the UVM Framework After the Workshop participants are able to use the UVM Framework API to create a testbench infrastructure for their own FPGA design.

  • Verification - approaches and methodologies
  • UVM - fundamentals and principles
  • UVM Framework - library components, structure and API

Requirements: Knowledge in SystemVerilog I Duration: 2 days I Language: English / optional German I Price: 1.250,00 EUR net

More information

Dates

  • 03. - 04.04.2019 | 9am – 5pm | Berlin, Germany

We are happy to offer further options such as live online sessions and on-site training upon request.

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