Due to the complexity of the UVM library, creating a testbench is a time consuming task and requires extensive knowledge of the capabilities offered by the library. To support verification engineers in the initial creation of a testbench infrastructure, the UVM framework was developed to create a UVM testbench very quickly. This can be simulated immediately and is adapted to the use case by making changes in some places using application specific code.
After a short introduction to some UVM classes and expressions, the workshop UVM TESTBENCH EASY quickly turns to the details of the UVM framework.
The course is aimed at verification engineers with no prior UVM knowledge who want to get started using UVM testbenches.
The goal of the course is to create a complete UVM testbench using the Siemens EDA UVM Framework (UVMF), which is then supplemented with application specific code in a few places.
has a masters degree in electrical engineering. From 1991 until the end of 2001, he worked as an ASIC design engineer at Philips Kommunikationsindustrie and Lucent Technologies in Nuremberg and at Infineon Technologies in San Jose, CA, USA. He worked on the creation of specifications, the implementation in VHDL, verification on module and chip level as well as programming of ASIC Driver Software in C.
Mr. Schwender has been working at TRIAS mikroelektronik GmbH since 2002 and, as the technical manager covers a large part of Siemens EDA's products - with a focus on HDL design, verification and cable harness design products.
Requirements: Knowledge in SystemVerilog I Duration: 2 days I Language: English / optional German I Price: 1.400,00 EUR net